Hierarchy levels for elements of modern analog/mixed signal VLSI can be represented as follows:
- Basic components (transistors, resistors, etc.);
- Basic analog and digital units (differential pairs, current sources, buffers);
- Functional blocks (amplifiers, filters, etc.);
- System blocks (RF front end, ADC, DAC, PLL);
- The complete system.
Besides, the individual components of the layout have their own internal hierarchy and structure, and they can also be divided into different regions (polygons). For example, a MOS transistor consists of the active region, gate region, connectors to metal regions, metal regions, etc.
Modern CAD suites do not require the user to design the layout of each component: the user only has to set up the parameters, and the CAD software will create the required component layout. In other words, individual components layout is designed using parameterized cell concept (PCELL).
It should be possible to use this approach for the design of the next level layout, i.e. for basic analog and digital unit design. Interconnections and geometrical configurations of the components in such units could be described using SKILL language Ч like polygon geometry is described for individual components.
This approach will save time and energy during layout design of basic, frequently used units.
Such parametrizable block libraries are now being developed for all advanced process technologies (primarily for 0.18Ц0.13 micron CMOS processes).