Standard Cell Libraries and ESD IO Libraries
Design and Characterization
Modern digital VLSI design methods are based on the use of standard cell libraries.
Such libraries may contain hundreds of different cells with relevant views (such as layout,
circuit schematic, verilog, vhdl, .lib, .lef, etc.).
Figure 1 illustrates standard cell library design flow. Its principal stages are:
- Creation, verification and optimization of cell circuit;
- Design, optimization and verification of cell layout;
- Library characterization and creation of additional views.
Figure 1. Standard cell library design flow
Data from each design stage needs to be verified before moving on to the next stage.
Characterization stage during which timing and power models for library cells are created is a special phase of logical cell library design.
Microproject company specializes in design and verification of standard cell libraries.
Automated verification system IP-Q is used for the following library verification levels:
- Physical (DRC, LVS, Antenna);
- Model (SPICEvs.Liberty, syntax check);
- Functional (test digital ASIC design);
The following items are included in the delivery:
1. Cells layout - GDSII, DFII
2. Cells circuit views – CDL, DFII
3. Extracted netlists – SPI, SPC
4. Timing and power models – Liberty, Synopsys DB, TLF
Additional representations (Astro views, EDIF, etc.) can be created at the customer’s request.