Engineering and maintenance of IP blocks
At present, engineering of systems-on-crystal makes wide use of technology based
on IP blocks as ready functional units for building up the whole system. Usage (sometimes more
often than once) of pre-designed IP blocks in SOC engineering is the main means of project
engineering acceleration, minimizing engineering mistakes and lowering the cost price of the system.
Today in Russia the intellectual property market is underdeveloped in this area,
although there is a large number of companies dealing with integrated chips, including SOC
engineering. These enterprises generally use IP blocks of their own design. Nevertheless,
it is not economically reasonable to develop IP blocks for every possible occasion, especially when
it concerns analog units. It is often more beneficial to acquire some parts of the system in the
form of IP blocks.
Company Microproject is directed at the development of a wide range of IP blocks,
their maintenance and the corresponding support services.
The business model for the sales of IP blocks is based on the “TRY & BUY” principle.
The Customer can first apply for the following kit:
- IP block datasheet;;
- Verilog-AMS behavioral model;;
- Encrypted netlist of the electrical circuit & the corresponding test bench;
- Layout abstract view, giving information about the size of the unit
and the position of the pins;
In this way before buying the IP the Customer can thoroughly study the product, up to own modeling of the project, they can also integrate the IP block into their system.
After the purchase, the Client receives a full documentation kit for the IP block,
in compliance with VSI Alliance standards, the electrical scheme, test equipment kit and the
Microproject also offers the service of integrating IP blocks into the Customer’s system,
as well as the necessary adjustment and correction of blocks in accordance with the specific requirements.
The time for engineering of IP blocks and integrated circuits is 1 – 6 months.